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The RESET input is not required for start-up but can be used to reset the MPU internal state and provide an orderly software start-up procedure. Refer to the Reset section for a detailed description. TIMER The TIMER input is used for clocking the on-chip timer, Refer to Timer section for a detailed description. AS (ADDRESS STROBE)
0
Address strobe (AS) is an output strobe used to indicate ::!*"!+w$$~ the presence of an address on the 8-bit multiplexed bus. The EXTERNAL CLOCK - An external clock should be apAS line is used to demultiplex the eight least significant ad- `t$~.~~$: ~lied to the OSCI input with the 0SC2 input not connected, ,. dress bits from the data bus, A latch controlled by address "~~ as shown in Figure 10. strobe should capture addresses on the negative edge,.+Thi@$' output is capable of driving one standard TTL load 4'&I130 LI (LOAD INSTRUCTION) ,$t,i,;, .Ki?:'~ %,$,\: 1,,.*,,., DS (DATA STROBE) .1,3 . $V.t, !},,,. This output is used to transfer data t@:~#$&& a peripheral or memory. DS occurs anytime the M~$U'@8s a data read or write. DS also occurs when the ~~~ ,{b'~k a data transfer to or from the MPU internal mw@.W,t%efer to Table 2 and b Figure 4 for timing charact6ri$J::$This output is capablef driving one standard T~&k~&and 130 pF. DS is a continuous signal at fosc,k+ 5~,#n the MPU is not in the WAIT or STOP state. S@&'@bus cycles are redundant reads of ~:,$:,il~ ` <. >y~L,,,:@$~
This output is used to indicate tha~ a fetch of the next opcode is in progress. LI remains low during an external or timer interrupt. The LI output is used only for certain debugging and test systems. For normal operations this pin is not connected. The LI output is capable of driving two standard LSTTL loads and 50 pF. This signal overlaps data strobe,
PAO-PA7 These eight pins constitute input/output port A. Each line is individually programmed to be either an input or output under software control via its data direction register as shown in Figure Ii(b). An 1/0 pin is programmed as an output when the corresponding DDR bit is set to a "l", and as an input when it is set to a "O'. In the output mode the bits are latched and appear on the corresponding output pins. An M PU read of the port bits programmed as outputs reflects the last value written to that location, When programmed as an input, the input data Mt(s) are not latched. An MPU read of the port bits programmed as inputs reflects the current status of the corresponding input pins. The 1/0 port timing is shown in Figure 3, See typical 1/0 port circuitry in Figure 11. During a power-on reset or external reset, all lines are configured as inputs (zero in data direction register). The output port register is not initialized by reset. The TTL compatible three-state output buffers are capable of driving one standard TTL load and 50 pF. The DDR is a re~d/write register.
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The A8-A12 output lines constitute the higher order nonmultiplexed addresses. Each output line is capable of driving one standard TTL load and 130 pF.
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The inter~al `memory spade is located within the first 128 " bytes of ,rnemory (first half of page zero) and is comprised of the "1/0 port locations, flmer locations, and 112 bytes of RAM. The MPU can read from or write to anj of,these loca~ ,tions. "A p~ogra,m write to on-chip locations is repeated on the external bus to permit off-chip"'memory to duplicate the content of on-chip me,mory. Program reads to on-chip ioca` tions also appear on theextern"al bus, but the MPU accepts ~~ data only from the addressed on-chip location, Any read
data appearing `on the''input bus. is ignored. The stack pointer is. used' to" address data stored on the stack. Data is stored on the stack during interrupts and subroutine calls. At power-up, the stack pointer is set to "$O07F and it ii' decremented as data is pushed onto the
,J ,., ...,
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stack. When data is removed from the stack, the stack ., pointar is incremented. A maximum of W bytes of RAM is
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for stack usage, Since most programs
use only a
`MEMOR~'ADDRESSING,
,small part of the allotted stack locations for interrupts and/or
; ,,subrouti,ne stacking purposes,' the unused bytes are usable
" The M CI%805E2 is `capable of'addressing 8192 bytes of' rn,amory and 1/0 registers, The address s"pace:is di~ded into internal memory space `and' external' memory: spacej as!"
shown in Figure 12. ,' ,, ,, ,' :,, ~~ q:. :., .";., , ,,. ,.; `~~~~~~~~ ~~ For ~~ ,,., .', ,. .,-. .. :..,' ,,. , . >, ; ..
for program data storage. ~" All memory locations above location $007F:are part of the
externalmemory map. In addition, ten'locations in the 1/0 portion of the lower 128 bytes of memory space, as shown in
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FIGURE 11 - TYPICAL PORT 1/0 CIRCUITRY
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I Data Direction Register Bit I
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1
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7
Data Direction Register DDA7
6 DDA6
5 DDA5
4 DDA4
3 DDA3
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O DDAO $0004
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Port .A Register
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PB3
PB2
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PBO
TABLE 3 - l/O PIN FUNCTIONS
T
R/~
DDR
l/O Pin Functions The 1/0 pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output to the 1/0 pin. The state of the 1/0 pin is read. The 1/0 pin is in an output mode, The output data latch is read.
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FIGURE 13 - PROGRAMMING MODEL
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stack#~;$s?],$ollowed
by PCH, etc. Pulling from the stack is in
`The stack pointer is a 13-bit r~&~,{3~~ontaining the -address of the next free location on~he ,fack. When accessing memory, the seven most sig@%~$<s are permanently set to 00~001. They are app~n~~d.~k the six least significant register bits to produce ~,,,a~ress within the range of $O07F to $0040, The stack ~fea bf&R'AM is used to store the return address on subrou&@ealls ~.. and the machine state during in,,~,..)'.,,v~, terrupts. Durin~%@~t&@b) or power-on reset, and during a "reset stack ~~t~.' instruction, the stack pointer is set to its upper li,,m~~W7F). Nested interrupts and/or subroutines may u~~,,.ti~~ts~~ (decimal) locations, beyond which the ,r ,! stack &oin@t'r'wraps around" and points :{ th:@~y~w.$&sing the previously stored ,:uB~@&*$fie call occupies two to its upper limit, information, A
carry occurs between bits 3 and 4 of the ALU duting an ADD or ADC instruction. The H bit is useful in binarv coded decimal addition subroutines. INTERRUPT MASK BIT (1) - When the I bit is set, both the external interrupt and the timer interrupt are disabled. Clearing this bit enables the above interrupts, If an interrupt occurs while the I bit is set, the interrupt is latched and will be processed when the I bit is next cleared.
NEGATIVE BIT (N) - When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative (bit 7 in the result is a logical one). ZERO BIT (Z) - When of the last arithmetic, CARRY set, this bit indicates that the result was zero,
RAM bvtes on the stack, while
.,.. .;,,
CONDITION CODE REGISTER (CC)
logical,
or data manipulation
BIT (C) - The C bit is set when duting
a carry or a borinstruction,
row out of the ALU occurs
an arithmetic
The condition code register is a 5-bit register in which each bit is used to indicate the results of the instruction just executed. These bits can be individually tested by a program and specific action taken as a result of their state. Each of the five bits is explained below, HALF CARRY BIT (H) - The H bit is set to a one when a
The C bit is also modified during bit test, shift,. rotate, and branch types of instruction, RESETS
The MC146805E2 has two reset modes: an active low external reset pin (R ES ET) and a power-on reset function; refer to Figure 5,
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The RESET input pin is used to re: en orderly' s'oftware start-up proc~ external reset mode, the RESET pin must sta~:low fc mum of one tRL. ,Thl trigger to improve it: :.
Freescale Semiconductor, Inc...
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FIGURE 15 - RESET AND INTERRUPT PROCESSING FLOWCHART
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07F+S P O+DDRS CLR l~Q Logic FF+Timer 7F;~Ts&ler ~
e
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The multiplexed address/data bus goes to the data input state (as shown in Figure 8). The high order address lines remain at the address of the next instruction, The MPU remains in the STOP mode until an external interrupt or reset occurs, During quests the STOP mode, to remove timer control any pending timer register timer (TCR) bits 6 interrupt reExternal and 7 are altered which is allowed to count in a normal sequence, The R/~ line goes to a high state, the multiplexed address/data bus goes to the data input state, and the DS and AS lines go to the low state (as shown in Figure 7). The high order address lines remain at the address of the next instruction. The MPU remains in this state until an external interrupt, timer interrupt, or a reset occurs, During the WAIT mode, the I bit in the condi~o~+,code register is cleared to enable interrupts. All oth~{~'rws?~rs, memory, may mode. FIGURE 17 - STOP FUNCTION FLOWCHART time, and 1/0 lines remain to allow interrupt If an external the external in their last st~~.t%~'timer exit ~b@&IW'e WAIT the same if the timer tb~n, be enabled a petiodic
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any further
interrupts,
interrupts are enabled in the condition code other registers and memory remain unaltered, remain unchanged.
register, All All 1/O lines
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stop
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Freescale Semiconductor, Inc...
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Stop Oscillator And All Clocks TCR Bit 7-O TCR Bit 6-1 Clear I Mask
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The M PU timer co~~*,&& single 8-bit software programmable counter wf~:~blt software selectable prescaler. Figure 19 sho~~,,~ b~&k diagram of the timer. The counter may be pre~~:~~der program control and decrements towards @i~When the counter decrements to zero, the timer ~~t~u~ request bit, i.e., bit 7 of the timer control regis@gF/~C~), is set. Then if the timer interrupt is not
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bit 6 of the TCR and the I bit in the condition are both cleared, the processor receives an in-
completion of the current instruction,
the pro-
e
stack, and then fetches the timer interrupt vector from locations $1FF8 and $1 FF9 in order to begin servicing the interrupt, If the MPU were interrupted vector fetch would while in the WAIT mode, the interrupt be from locations $1 FF6 and
$IFF7. The counter continues to count after it reaches zero, allowing the software to determine the number of internal or external input clocks since the timer interrupt request bit was set. The counter may be read at any time by the processor without disturbing the count. The content of the counter becomes stable prior to the read portion of a cycle and does not change during the read. The timer interrupt request bit remains set until cleared by the software. If a read occurs before the timer interrupt is serviced, the interrupt is lost. TCR7 may also be used as a scanned status bit in a noninterrupt mode of operation (TCR6= 1). The prescaler is a 7-bit divider which is used to extend the maximum length of the timer. Bit O, bit 1, and bit 2 of the TCR are programmed to choose the appropriate prescaler output which is used as the counter input. The processor cannot write into or read from the prescaler; however, its contents are cleared to all "OS" by the write operation into TCR when bit 3 of the written data equals 1, which allows for truncation-free counting. The timer input can be configured for three different operating modes, plus a disable mode, depending on the value written to the TCR4, TCR5 control bits. Refer to the Timer TIMER Control INPUT Register MODE section.
Turn on Oscillator Wait for Time Delay to Stabilize
Fetch External Interrupt or Reset Vector
%
WAIT The WAIT instruction places the MC146805E2 in a low power consumption mode, but the WAIT mode consumes
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somewhat more power than the STOP mode; refer to Table 1. In the WAIT function, the internal clock is disabled from all internal 18, Thus, circuitry all internal except the timer circuit; refer to Figure except the timer processing is halted
1
to a "U', the inand the external mode can be
If TCR4 and TCR5 are both programmed put to the timer is from an internal clock TIMER input is disabled. The internal
clock
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FIGURE19 - TIMER BLOCK DIAGRAM Selected by TCR4, TCR5 Selected by TCRO, #
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Internal Clock [ Cleared by TCR3
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TIMER CONTROL REGISTER (TCR) 7654 TCR7 TCR6 TCR5 TCR4 321 TCR3 TCR2 TCRI
,$'.\JeR5 .:,. ~:,':,. ""' .'>$(.!i<\; o ~, .,.*) .. 0 t:."t:-.~,,+?, o to-.\,..?:* TCRO "'~; ,.*': 1 ` a1
TCR4 0 1 0 1 Internal clock (AS) to timer AND of internal clock (AS) and TIMER pin to timer Inputs to timer disabled TIMER pin to timer
1 - Set whenever the counter dqc~~~~ `"$:,,* \ der program control. ,:~t: ,,/$ym f* O - Cleared on external rese$:lp~~er-on struction, or progra~''w~bl
to zero, or unreset, STOP in-
TCR3 - Timer Prescaler Reset bit: wtiting a "l" to this bit resets the prescaler to zero. A read of this location always indicates a "O" (unaffected by RESET).
TCR2, TCRI, TCRO- Prescaler address bits: decoded to select one of eight outputs of the prescaler (unaffected by RESET).
TCR2 o
TCR1 0
TCRO I Result +1 0
0
o 0 1 1 1 1 " 1 - Select external clock source. O - Select internal clock source (AS).
0
1 1 0 0 1 1
1
0 1 0 1 0 i
+2 +4 +8 -16 +32 -64 +128
INSTRUCTION
SET
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TCR4 - External enable bit: control bit used to enable the external TIMER pin (unaffected by RESET). 1 - Enable external TIMER pin. O - Disable external TIMER pin.
The MPU has a set of 61 basic instructions. They can be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The following paragraphs briefly explain each type. All the instructions within a given type are presented in individual tables.
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5es of the processor are sed to indicate "contents is replace-d by, " and a colon indi.
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:.r6aiSteror acct)mulator,
to ex~the opcode. Operations
and no
Freescale Semiconductor, Inc...
RAM and 1/0 registers
chip ROM, Direct addressing is ef-
1)
addrassof in the"two bytes following the opextended addressing modes are urnents anywhere in memory with ction. When using the Motorola ]ot specify whether an instruction ?d addressing, The assembler
nest efficient addressing mode,
ing mode, theeffective
(PC+2);PC+PC+3
1); Address Bus Low-(PC + 2)
;t :addressing mode, the effective is contained in the 8-bit index is addressing mode can access the first 256 instructions are only one byte move a pointer through a table or erenced RAM or 1/0 location.
)y,adding th,e contents of the byte ]t of the index register; therefore, nywhere, within the lowest 511 mple, thi,s mode of addressing is th element in an n element table. vtes. The contents of the index ntents of (PC+I) is an le bvte "offset indexing permits in either RAM or ROM,
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INDEXED, 16-BIT OFFSET opcode. The bit set and clear instructions occupy two bytes, one for the opcode (including the bit number) and the second to address the byte which contains the bit of interest. EA=(PC+I); PC~PC+2 Address Bus High YO; Address Bus Low+(PC BIT TEST AND BRANCH
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In the indexed, 16-bit offset addressing mode the effective address is the sum of the contents of the unsiged 8-bit index register and the two unsigned bytes following the opcode. This addressing mode can be used in a manner similar to indexed 8-bit offset, except that this three byte instruction allows tables to be anywhere in memory (e.g., jump tables in ROM). As with direct and extended, the M6805 assembler determines the most efficient form of indexed offset - 8 or 16 bit. The content of the index register is not changed. EA=X+[(PC+ I):(PC+2)]; PC+PC+3 Address Bus High-( PC+ 1)+ K Address Bus Low+K+ (PC+2) where: K = The carry from the addition of X + (PC + 2) RELATIVE
+ 1)
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Relative addressing is used only in branch instructions. In relative addressing the content of the 8-bit signed byte following the opcode (the offset) is added to the PC if and only if the branch condition is true, Otherwise, control proceeds to the next instruction. The span of relative addressing is limited to the range of - 126 to + 129 bytes from the branch instruction opcode location, The Motorola assembler calculates the proper offset and checks to see if it is within the span of the branch.
Bit test and branch is a combination of direct ad~$$$~g, bit addressing, and relative addressing. The bit ,@d~% and condition (set or clear) to be tested are part ~f,%$<~pcode. The address of the byte to be tested is in tQ@:~~~&byte immediately following the opcode byte,~ .4. \\*f\i... \
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CONFIGURATION . f":$~sTEM Figu~~,*~firough 25 show in general terms how the M C~468~52 bus structure may be utilized. Specified interEA= PC+2+ (PC+ 1); PC~EA if branch is taken; fat~{~etails vary with the various peripheral and memory otherwise, PC+ PC+ 2 #~&c~k emnloved. :%~t,i~$.$able11 pro~ides a detailed description of the information BIT SET/CLEAR ~t~~'!~$,present on the bus, read/write (R/~) pin and the load inDirect addressing and bit addressing are combined in in`":S struction (Ll) pin during each cycle for each instruction. structions which set and clear individual memory and MO Y> This information is useful in comoaring actual with expetted results during debug of both softw~re and hardware as the control,, program is executed. The information is categorized in groups according to addressing mode and number of cycles per instruction.
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Branch Always Branch Never
TABLE6-
BRANCH INSTRUCTIONS Relative Addressing Mode # Cycles 3 3 3 3 3 3 3 3 3 "!$,?<< skr.\:27,, ,* `~,;:": ,?*., ,,$''" ~.,, .;3>::> ~t.,.?: ~i:\, ~<$.it ,,l.,.,~,i,.,. ., ,y..,.1. l!? ., ,.,,.
Function
Mnemonic BRA BRN BHI BLS BCC (BHS) BCS (B LO) BNE BEQ BHCC BHCS
I
Op Code 20 21 22 23 24 24 25 25 26 27 28 29
t
# Bytes 2 2 2 2 2 2 2 2 2 2
Branch IFF Higher Branch IFF Lower or Same Branch IFF CarrV Clear (Branch IFF Higher or Same) Branch lFFCarrV Set (Branch IFF Lower) Branch lFF Not Equal Branch IFF Equal Branch lFF Half CarrV Clear
:;~:*'&""" ,g ~,, <$ . .$, ~, " y,
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Branch lFF Half CarrV Set Branch IFF Plus Branch lFF Minus
2 ", k~%$>, 2 +$ci'y<;& ` ~:w~ `;@ 3 I `::$2:Y*I 3 3 3 3 3 6 I
BPL BMI
2A 2B
3
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,..~k.;,
Function Branch IFF Bit nis Set Branch IFF Bit n is Clear Set Bit n Clear Bit n qR~3:&'rh = 0.. .7) +,,B'%$F%n[n= O...7) "'" ,l:t~ %@~R n (n= O...7) ,.,:,1 ,{, *, ~.t. `*?t . ~$% Mne~'~~J$k$ Bit Set/Clear Op Code - - 10+2*n ll+2*n # Bytes - -- 2. 2
Addressing Modes Bit Test and Branch # CVcles - -- 5 5 Op Code 2. n 01+2*n -- -- # Bytes 3 3 -- -- # Cvcles 5 5 -- --
Function Transfer A to X Transfer X to A Set CarrV Bit Clear CarrV Bit Set Interrupt Mask Bit Clear Interrupt Mask Bit Software Interruot
Mnemonic TAX TXA SEC CLC SEI CLI Swl
Op Code 97 9F 99 9a 9B 9A a3
# Bytes 1 1 1 1 1 1 1
# Cycles 2 2 2 2 2 2 10
~ Wait
WAIT
aF
1
2
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TABLE 10 - MCI=5 CMOS INSTRUCTION SET OPCODE MAP
Bit Manipulation BTB BSC Hi LOW 0 1 0321 2 0310 @ 3 ml 1 m BR S ET05 BTB BRCLR05 aTB BRSET15 BTB ml BSETO 5 BSC BCLRO 5 BSC 5 BSET1 2 asc 5 BCLR1 BSC 2 5 BSET2 2 BS: 2 2 BCLR2 BSC 5 B S ET3 W1O
3
Branch REL
Read-Modify-Wtite
Control 1X1 0110 1;
0111
DIR
ml 1 5 NEG
INH 4 01w 3 NEG DIR 1 INH 1
l~H 0101 3 NEG INH 2
INH 8
lm
INH 9
lml
IMM 1$0 2 2
DIR B
1011
,.>S%&T $>' F ./::. .$ ,,?
.+ !s,, $~m
I&
1101 5
lx 1
1170 4
IF Hi
1111
6 NEG 1X1 1
5
9 RTI 1 RTS INH 6 INH
BRA 2 BRN 2 BHI
2
NEG
lx
REL 3 REL 3 REL 3 BLS
2
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3
1
3
SUB IMM 2 2 CMP `?#&,; lhlM,. ~!!a . 2 ,*`"'~$ 3 SB &;; i :$ ~Y%c , ,J~~> DIR 2
":\. >" 4 SUB `$?* ,$S U B .&, ~, ~~, \+~ EXT : cMp SBC 3 CPX 3 AND 3 BIT 3 LDA EXT 4 EXT 4 EXT 4 EXT 4 4 EXT 4
.. .
3 SUB o lx 3 CMP lx SBC 1 ml 2 0310 3 0311 4 Olw 5 0101 1 I
SUB 3 CMP 3 SBC 3 CPX 3 AND 3 BIT 3 LDA 1X2 5 2 1X2 5 2 1X2 5 2 1X2 5 2 1X2 5 2 1X2 5 2
SUB 1X1 4 CMP 1X1
4
SBC 1X1 4 CPX 1X1 4 AND 1X1 4 BIT 1 4 LDA 1 1 1 1
lx CPX lx 3 AND lx 3 BIT lx 3 LDA
5 COM COMA DIR 5 LSR DTR 1 LSRA 1 2 2
3 INH 3 INH
3
BRCLR15 BTa B R S ET25 BTB
2 BCC 2 BCS 2 BNE
REL 3 REL 3 REL 3
o 0 0
~ a ! Mm +m 3 -. 0 3 $
s
4 Olw
3
3 COMX INH 3 LSRX 1 INH 1
6 COM 2 LSR 2 1X1 1 1X1 6 1 LS R COM
5 Swl lx 5 lx 1
10 INH
5 0101
3
BRCLR25 BTB B R S ET35
5 ROR RORA
3 RORX 1
3 ROR
6
5
6 0110 0111 7
ROR
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1X2
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TABLE 11 - SUMMARY Cycles Cycle #
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OPERATION R/w Pin LI Pin
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Data Bus
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Freescale Semiconductor, Inc.
TABLE
11 -
SUMMARY
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OPERATION
(CONTINUED)
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Address Mode Instructions 8-Bit Offset
Cycles
Cvcle # I
Address
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1
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5
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1 1 1 1 1
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PACKAGE DIMENSIONS
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